In the manufacturing of chip packaging, attempts have been made to maintain efficient interconnection between the die and other components as die and pad densities increase at a dramatic rate and geometries decrease at an equally dramatic rate. The technology roadmap for semiconductor packaging has technical drivers which describe meticulous efforts to bring the die closer to other components through thinner and denser chip packaging to achieve higher finished system functionality. In one such effort, a semiconductor package is sometimes eliminated and the die are placed directly on the printed circuit in a flip-chip process which often uses die that have been prepared for placement through a process known as “Chip Scale Packaging” or CSP.
Chip Scale Packaging involves preparing a semiconductor die with appropriate dielectrics and conductive bumps on the active site of the die so that the die is properly prepared to attach to another interconnect such as a printed circuit board. FIG. 1 a cut-away view of a prior art process through which an individual die undergoes bumping and dielectric coating, wherein the assembly is subsequently bonded to a substrate and the conductive bumps break through an adhesive to make electrical contact to the substrate, thereby completing a chip package. This preparation does not typically extend the physical dimensions of the die in length or width, which has given rise to the term “Chip Scale” for such a preparation.
In an effort to keep up with Moore's Law in Semiconductors, which predicts higher interconnection densities over time, a lot of focus has been spent on Chip Scale Packages to achieve thinner, denser packages and escape routing. Escape routing is the process of interconnecting close proximity die bond pads with mating bond pads in the chip package or the printed circuit board on the applied dielectrics of the CSP. The pitch on the die maybe at 75 microns and the closest pitch obtainable on the printed circuit may be 250 microns. The work of providing escape routing through circuitry on the Chip Scale package becomes difficult as geometries keep shrinking. Chip Scale Packaging has evolved the technologies of Build-up and Redistribution to assist in this escape routing.
Build-up processes and Redistribution technology places dielectrics external to the active wafer or die surface for the Chip Scale Package, usually through a spin coating process in the wafer fab, followed by formation of holes in the dielectric usually through a photoimaging process. The wafer and dielectric then proceeds through a metallic sputtering process to apply a conductor to achieve interconnect vias through the holes in the dielectric and conductive material on the surface. The surface metal is then chemically milled to a circuitry pattern utilizing another photoimaging process thereby completing the external circuitry for a first metal layer on the wafer or die for the Chip Scale Package. After this process the wafer is sawed to release the Chip Scale Package which includes a singulated die.
The state-of-the art in Chip Scale Packaging is the use of multiple layers of metallization and multiple layers of the dielectric to achieve the highest density microelectronic package. This forms a multilayer interconnect and this multilayer process is called Build-up because each dielectric is added sequentially. For formation of more than one metal layer, the process of spinning on a dielectric, forming via holes, metallization and photoimaging is repeated. The Build-up process is commonly utilized in the printed circuit and chip packaging manufacturing arenas for multilayer interconnects and is now being used in very dense packages where the Build-up process begins on the surface of the active silicon. These interconnects and packages are sometimes referred to as Wafer Scale Packaging (WSP). FIG. 2 is a cut-away view of a prior art process through which a multilayer package is prebuilt without a die, wherein an access port is etched in the substrate revealing the connections for the die, the die is placed in the access port, and the structure is bonded together. FIG. 3 is a cut-away view of a prior art process through which a die is positioned and bonded in an access port of a substrate, wherein the dielectric layers and via interconnects are built on top of this structure.
Another multiple die version of Chip Scale Packaging is sometimes referred to as build-up on die or System-In-Package (SIP). Intel Corporation developed a version of build-up on die referred to as BBUL. FIG. 4 is a cut-away view of a prior art build-up on die process utilizing a carrier tape to position the die, wherein the carrier tape is subsequently removed and copper/dielectrics are deposited to form individual layers in a process similar to the Intel Corporation BBUL process. This technology is an extension of Chip Scale Packaging and first locates multiple die on an adhesive tape or similar substrate and molds an encapsulant to secure the die in place. After removing the adhesive tape, a series of dielectrics and conductive layers are built upon these initial die thereby forming the chip to chip interconnect structure. There are benefits to the build-up on die process over typical chip packaging because of the close proximity that is possible with the die and the interconnections. This closer proximity provides improved electrical performance due to lower inductance of the vias and improved signal integrity because signals from die to die travel a shorter distance.
Complex build-up on die processing suffers from technological constraints due to reliability and quality issues when temperature excursions (as in soldering) cause fractures in the composite which are due to Coefficient of Thermal Expansion (CTE) differences between the various materials and components of the package. These issues are even more problematic when attempts are made to package multiple die of different geometries and materials in a monolithic structure. For example, encapsulation materials of the embedded die and the design of the vias often result in an undesirably rigid structure which, combined with the CTE mismatch materials, causes delamination (adhesion failure) during a thermal stress or soldering operation. Furthermore, the embedding of various components, such as sensors, MEMs (Micro Electromechnaical Machines), capacitors, resistors, inductors, transducers and antennas, each of which typically has a unique CTE, cannot be performed in multicomponent structures due to additional stress issues of the various materials and their different CTE values.
Another shortcoming of existing art is that it does not accommodate various component thicknesses during a multilayer structure embedding process because the build-up process requires a very level surface for the first dielectric and metal layers to be successful. Various die thicknesses would be typical in a high speed system because more than one material is used for the wafer processing. High Speed systems may have multiple die fabricated with two different materials such as Gallium Arsenide (GAAS) and Silicon Germanium (SiGe). Each of these die substrate materials would have with their respective thickness profiles and the thickness difference's would not be suitable for existing build-up on die processes.
Still another shortcoming of build-up on die prior art is that it does not facilitate die electrical testing prior to embedding. Semiconductor wafer processing techniques are known to have defects that are undetectable unless tested, and testing often occurs after the die is packaged. In a build-up on die process, if a die is defective, the entire monolithic structure will be wasted because testing cannot be performed very early in the process. Only known good die (KGD) can be used with prior art build-up on die processes.
Build-up on Die and Chip Scale packaging do not accommodate optical transmission of data between chips in either discrete component technologies or in monolithic technologies. As digital broadband increases its bandwidth and microprocessor speeds increase, there are technology drivers to utilize optical waveguides, embedded optical components and solid state monolithic structures for die-to-die, or die-to-component interconnect structures. The bandwidth limit for copper transmission of digital signals, for example, is between 600 Megabits/second and 10 Gigabits/second depending on the circuit design and the absorbance of the dielectric materials. Optical signal transmission can increase available bandwidth to several times copper wire bandwidth. Existing build-up on die techniques do not accommodate the direct connection of optical components for die-to-die or component-to-component optical interconnections to tap into these higher bandwidths.
Build-up on die and Chip Scale packaging also have difficulty addressing thermal dissipation requirements of monolithic structures. Multiple die are typically placed in closer proximity to leverage the performance gains associated with such placement. However, as performance increases, the die dissipate more heat energy during operation, and consequently a means of dissipating the heat to an external cooling source either passively by conduction or with an active system becomes more critical. Existing buildup on die and CSP technologies have difficulty in removing excess heat during operation of the system.
Typically, build-up on die and chip scale packaging utilize copper vias with various configurations such as plated-through-holes, blind vias, buried vias, or microvias for interconnecting the die and the copper circuitry in a package. These vias connect one circuitry layer (sometimes referred to as metal layer) to the next. These vias are usually formed 90 degrees to the plane of the circuitry, die, or dielectrics.
Although commonly used, sharp, 90 degree structures have several disadvantages when utilized unilaterally throughout a structure in high speed, high density designs. Both electrical signals and optical signals experience significant signal loss at a 90 degree bend. Electrical signals radiate significant amounts of energy and noise at the 90 degree bend thereby degrading the signal. Optical signals experience a more difficult hurdle because a relatively large percentage of the incoming optical light is reflected back to the source, never making the bend. Also, 90 degree angles are sometimes not the optimum escape design routing from the very tight pitch on the die to wider pitched components on other components. For example, a die could have a 75 micron pitch or distance between bonding pads. A printed circuit board may have a 250 micron pitch. A typical design may take three circuitry layers and three dielectric layers to connect these bond sites utilizing 90 degree vias. As the mismatch between the pitch of the die and the component increases, the likelihood of requiring more circuitry layers increases with 90 degree vias, thereby increasing the cost of the system. In addition, 90 degree vias exhibit high degrees of stress between the via and the copper circuitry during a thermal excursion due to the CTE mismatch of copper circuitry and the dielectric materials. Cracks often initiate at the interface between the via and copper circuitry which can result in a circuitry failure and an electrical open circuit.